Proposition of a benchmark for evaluation of cores mapping onto NoC architectures
نویسندگان
چکیده
Complex application specific SoC are often based on the NoC approach [1]. NoC are under investigation since several years and many architectures have been proposed[2]. Generic NoC are often proposed with their synthesis tool in order to rapidly tailor a solution for a specific application implementation [4][5]. The optimised mapping of cores on a NoC [3] and the optimised NoC configuration in terms of topology, FIFO and link sizes for instance is a new research area which is now investigated deeply. Validation and evaluation of solutions is often conducted through simulations for deterministic applications. Comparisons between proposed optimisation approach is difficult as they use their own evaluative application. Benchmarking is a classical solution to normalize comparisons. We are proposing in this paper a set of application tasks behaviours in order to evaluate NoC topologies as well as NoC core mapping techniques. We illustrate this benchmark proposition on a specific NoC simulation. Index—SoC, IP, 4G, NoC, benchmark.
منابع مشابه
Application Mapping onto Network-on-Chip using Bypass Channel
Increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. NoCs have features such as scalability and high performance. NoCs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made NoC. Due to increasing number of cores, the placement of the cores i...
متن کاملDesign of a novel congestion-aware communication mechanism for wireless NoC architecture in multicore systems
Hybrid Wireless Network-on-Chip (WNoC) architecture is emerged as a scalable communication structure to mitigate the deficits of traditional NOC architecture for the future Multi-core systems. The hybrid WNoC architecture provides energy efficient, high data rate and flexible communications for NoC architectures. In these architectures, each wireless router is shared by a set of processing core...
متن کاملReliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)
Nowadays, faults and failures are increasing especially in complex systems such as Network-on-Chip (NoC) based Systems-on-a-Chip due to the increasing susceptibility and decreasing feature sizes. On the other hand, fault-tolerant routing algorithms have an evident effect on tolerating permanent faults and improving the reliability of a Network-on-Chip based system. This paper presents reliabili...
متن کاملMultiple Vdd on 3D NoC architectures
The communication problem is a challenge issue for Integrated Circuits (ICs), which usually becomes a bottleneck for performance improvement. Three-dimensional integration (3D), as well as network-on-chip (NoC), are two recent design approaches that promise to alleviate the consequences of interconnection degradation. This paper introduces a new methodology for powerefficient application mappin...
متن کاملTowards Dilated Placement of Dynamic NoC Cores
Instead of mapping application task graphs in a compact manner onto reconfigurable devices using a network-on-chip for interconnecting application cores, we propose dilating the mappings as much as the available latencies on critical connections allow. In a dilated mapping, the unused resources between an application’s configured components can be used to provide additional flexibility when the...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2005